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ds-25dn512c?037a?1/2014 features ? sing le 2.3v - 3.6v supp ly ? serial peripheral inte rf ac e ( s p i ) co mp a ti b le ? supp ort s spi mode s 0 an d 3 ? su p p o r t s d u al o u tp ut r e ad ? 85mhz maximum ope r ating f r e que ncy ? clo ck-to-output (t v ) o f 7 ns ? fl exibl e , optimized erase architecture fo r co de + da t a s t o r age app lication s ? uni f o r m 256 -byte page e r ase ? unifor m 4-kbyte block er ase ? uni f o r m 32-kbyte block erase ? fu ll chi p era s e ? hard ware control l ed lo cki ng of pro t ected sectors via wp pin ? 128 -byte progra m mab l e ot p se curity re gister ? flexible pr ogramming ? byte /pa ge program (1 to 25 6 bytes) ? fa st program and erase t i me s ? 1.5ms t y pical pag e pro g ram (256 byte s) t i me ? 50ms t y pi ca l 4-kbyte bl ock erase t i me ? 400 ms t y p i cal 32-kb yte block erase t i me ? automatic checkin g and rep o rting of era s e/pro g ram fai l ures ? sof t wa re controll ed reset ? jedec s t and ard manufacturer and d e vice id re ad method olog y ? l o w po we r di ssi p a ti on ? 200 na ultra d eep pow e r do wn current (t ypical ) ? 5a dee p power-do w n current (t ypical ) ? 25u a s t andb y curre nt (t ypi c al) ? 5ma active re ad curren t (t ypica l ) ? endu rance: 100,00 0 pr o g ram/era s e c y cl es ? dat a retentio n: 2 0 y ears ? compl i es with fu ll in dustrial t e mpe r a t u r e rang e ? industry s t and ard gree n (pb / ha lide - fr ee /r ohs compli ant) pa cka ge op ti ons ? 8-le ad soic (150-mil ) ? 8-p a d u l tra t h in d f n (2 x 3 x 0.6 mm) ? 8-lead tssop package a t 25dn512c 512-kbit, 2.3v minimum spi serial flash memory with du al-i/o support advance datasheet http://
2 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 1. description the adesto ? at25dn5 12c is a serial interf ac e flash memory device des igned fo r use in a wide variety of high-volume consumer based applications in which program code is shadowe d from fla s h memory into embedded or external ram for exec u tion . the flexible erase arc h itecture of the AT25DN512C, with its page eras e granularity it is ideal for d a ta storage as well, eliminatin g the need for additional data storage devices. the erase block sizes of the at25dn51 2 c have been optimized to meet the needs of today's code and data storage applications. by optimizing the size of th e erase blocks , the memory s p ac e can be used muc h more efficiently. because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large sectored and large block era s e flash memory devices can be greatly reduced. this increased memory s p a c e efficiency allows additional code routines and data storage s e gments to be added while still maintaining the same overa l l devic e density. the device also conta i ns a s p ec ialized otp (one-time programmabl e) security register that can be used for purposes such as unique device serialization, system-level electronic se ri a l number (esn) storage, locked key storage, etc. speci f ically designed for us e i n many different systems, the AT25DN512C supports re ad, progra m , and erase operations wi th a wide supply voltage range of 2.3 v to 3.6v. no separ ate voltage is required for programming an d erasing. 2. pin des c riptions and pinout s t a ble 2-1. pin desc ription s symbol name and function as serte d st ate type cs chip select : asserti ng th e cs pin selects the device. when the cs pi n is d easserted, the d e vice will be desel ected a nd n o rmall y be place d in st a ndby mo de (n ot dee p powe r-down mo de), an d the so p in wi ll b e in a h igh-imp edan ce st ate . when t he d e vice i s desel ected, dat a w ill not be accepted on the si pi n. a high-to-lo w tran si ti on on the cs pin is requ ired to st art a n opera t i on, a nd a low - to-h igh transition is re quire d to en d an ope ration. whe n endi ng an in te rn all y sel f -timed op eration such as a prog ram or erase cycl e , the de vice will n o t en te r the st a ndb y mod e u n til th e completio n of the op eration . low input sck serial cl ock : t h is p i n is u sed to pro v i de a cl ock to th e de vi ce and is used to control the flo w of dat a to a nd fro m the de vi ce. co mm an d, a ddress, a nd inp u t d a t a p r esent on th e si pin i s al ways latched i n o n th e ri sing ed ge of sck, whil e output dat a on the so pin i s al ways cl ocked ou t on the fa llin g edge o f sck. - input si (i/o 0 ) serial input : th e si pin is used to shi f t da t a i n to the d e vice. t he si pi n is u s ed for a ll d a t a inp u t inclu d in g co mman d and ad dress seque nces. d a t a o n the si pin is alw a ys l a tch ed in on the risin g edg e o f sck. with the dua l -ou t p u t read command s, the si pi n be comes an outpu t p i n (i/o 0 ) in con jun ctio n wi th other pin s to allo w two b i t s of d a t a on (i/o 1- 0 ) to be clocke d out on every fa llin g edge o f sck. t o mai n t a in co nsistency w i th the spi nomencl a ture, the si (i/o 0 ) pin wil l be referen ced a s the si p i n unl ess spe cifically ad dressing the du al-i/o mo des in whi c h ca se i t wil l be referenced a s i/o 0. dat a presen t on the si pi n will be i gnore d when ever th e d e vice is dese l ected (cs is deasserted). - input/ output so (i/o 1 ) serial out p ut : t he so pi n is u s ed to sh if t dat a out fr om the device . dat a on the so pi n i s alwa ys clo c ke d out o n th e fal ling e dge o f sck. with the dua l -ou t p u t read command s, the so pi n remai n s an outpu t p i n (i/o 1 ) i n con j un ctio n wi th other pin s to allo w two b i t s of d a t a on (i/o 1- 0 ) to be clocke d out on every fa llin g edge o f sck. t o mai n t a in consistency with th e spi no me nclat u re , th e so (i /o 1 ) p i n will be referen ced as the so pin un less specifical ly a ddre s si ng th e dual -i/o m odes in w h ich case it w ill be referen ced as i/o 1. th e so pin wil l be in a hig h -impe dance st at e whenever the d e vice is desel ected (cs is deasserted). - input/ output
3 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 wp write protect: the wp pin controls the hardware locking feat ure of the device. please refer to ?protection commands and features? on page 12 for more details on protection features and the wp pin. the wp pin is internally pulled-high and may be left floating if hardware c ontrolled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input hold hold: the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pi n is asserted, transitio ns on the sck pi n a nd d a t a o n the si pin wi ll be ign o red , and the so p i n will b e in a high -imped ance st a t e . the cs pin must be asserted, and the sck pin must be in the low state in orde r for a hold condition to start. a hold condition pauses serial commu nication on ly and does not have an effect on i n te rnally sel f -timed operati o ns such as a p r ogram or erase cycle. pl ease refer to ?hold? on page 27 for additional details on the ho ld o peration. the hold pin is internally pulled-high and may be left floating if the hold f unction will not be used. however, it is recommended that the hold pin also be externally connected to v cc whenever possible. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. - power gnd ground: th e groun d refe rence for the p o wer supp ly . gnd sh ould b e conne cte d to the system ground. - power t a ble 2-1. pin desc ription s (con tin u e d ) symbol name and function as serte d state type f i gu re 2-1 . 8 - soi c to p vie w figure 2-2. 8-tssop top view fi gu re 2-3 . 8-udfn (top view) 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si cs so wp gnd 1 2 3 4 8 7 6 5 vcc hold sck si
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5 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 4. memory array to provide the greatest flexibility, the memory array of the AT25DN512C can be erased in three levels of granularity including a full chip erase. the size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. the memory architecture diagram illustrates the breakdown of each erase level. fig u re 4 - 1. memo ry arc h itectu r e diagr a m 5. device operation the AT25DN512C is controlled by a set of instructions that are sent from a host controller, commonly referred to as the spi master. the spi master communicates with the at25dn 512c via the spi bus which is comprised o f four signal lines: chip select ( cs ), serial clock (sck), serial in put (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the AT25DN512C supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 5-1. spi mode 0 and 3 32kb 4kb 1-256 byte block erase block erase page program (52h command) (20h command) (02h command) 4kb 00ffffh ? 00f000h 256 bytes 0 0ffffh ? 00ff00h 4kb 00efffh ? 00e000h 256 bytes 00feffh ? 00fe00h 4kb 00dfffh ? 00d000h 256 bytes 00fdffh ? 00fd00h 4kb 00cfffh ? 00c000h 256 bytes 00fcffh ? 00fc00h 4kb 00bfffh ? 00b000h 256 bytes 00fbffh ? 00fb00h 4kb 00afffh ? 00a000h 256 bytes 00faffh ? 00fa00h 4kb 009fffh ? 009000h 256 bytes 00f9ffh ? 00f900h 4kb 4kb 4kb 006fffh ? 006000h 256 bytes 0006ffh ? 000600h 4kb 005fffh ? 005000h 256 bytes 0005ffh ? 000500h 4kb 004fffh ? 004000h 256 bytes 0004ffh ? 000400h 4kb 003fffh ? 003000h 256 bytes 0003ffh ? 000300h 4kb 002fffh ? 002000h 256 bytes 0002ffh ? 000200h 4kb 001fffh ? 001000h 256 bytes 0001ffh ? 000100h 4kb 008fffh ? 008000h 007fffh ? 007000h 000fffh ? 000000h 256 bytes 0000ffh ? 000000h block erase detail page program detail page address block address range range 32kb 32kb ? ? ? sck cs si so msb lsb msb lsb
6 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 5.1 dual output read the atx features a dual-output read mode that allow two bits of data to be clocked out of the device every clock cycle to improve throughput. to accomplish this, both the si and so pins are utilized as outputs for the transfer of data bytes. with the dual-output read array command, the si pin becomes an output along with the so pin. 6. commands and addressing a valid instruction or operation must always be started by first asserting the cs pin. after the cs pin ha s been asserted, the host controller must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction depende nt information such as address and data bytes would then be clocked out by the host controller. all opcode, a ddress, and data bytes are transferred with the most-significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not supported by the AT25DN512C will be ignored by the device and no operation will be started. the device will continue to ignore any data presented on the si pin until the start of the next operation ( cs pin being deasserted and then reasserted). in addition, if the cs pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of three bytes of information to be sent, representing address bits a23-a0. since the upper address limit of the AT25DN512C memory ar ray is 00ffffh, address bits a23-a16 are always ignored by the device. table 6-1. command listing command opcode clock frequency address bytes dummy bytes data bytes read commands read array 0bh 0000 1011 up to 85 mhz 3 1 1+ 03h 0000 0011 up to 33 mhz 3 0 1+ dual output read 3bh 0011 1011 up to 70 mhz 3 1 1+ program and erase commands page erase 81h 1000 0001 up to 70 mhz 3 0 0 block erase (4 kbytes) 20h 0010 0000 up to 70 mhz 3 0 0 block erase (32 kbytes) 52h 0101 0010 up to 70 mhz 3 0 0 d8h 1101 1000 up to 70 mhz 3 0 0 chip erase 60h 0110 0000 up to 70 mhz 0 0 0 c7h 1100 0111 up to 70 mhz 0 0 0 chip erase (legacy command) 62h 0110 0010 up to 70 mhz 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 up to 70 mhz 3 0 1+ protection commands write enable 06h 0000 0110 up to 70 mhz 0 0 0 write disable 04h 0000 0100 up to 70 mhz 0 0 0 security commands program otp security register 9bh 1001 1011 up to 70 mhz 3 0 1+
7 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 7. read commands 7.1 read array the read array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address is specified. the device incorporates an internal address counter that automatically increments every clock cycle. two opcodes (0bh and 03h) can be used for the read array command. the use of each opcode depends on the maximum clock frequency that will be used to read data from the device. the 0bh opcode can be used at any clock frequency up to the maximum specified by f clk , and the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (0bh or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, an additional dummy byte needs to be clocked into the device if the 0bh opcode is used for the read array operation. after the three address bytes (and the dummy byte if us ing opcode 0bh) have been clocked in, additional clock cyc les will result in data being output on the so pin. the da ta is always output with the msb of a byte first. when the last byte (00ffffh) of the memory array has been read, the devic e w ill continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the so pin into high-impedance state. the cs pin can be deasserted at any time and does not require a full byte of data be read. read otp security register 77h 0111 0111 up to 70 mhz 3 2 1+ status register commands read status register 05h 0000 0101 up to 70 mhz 0 0 1+ write status register byte 1 01h 0000 0001 up to 70 mhz 0 0 1 write status register byte 2 31h 0011 0001 up to 70 mhz 0 0 1 miscellaneous commands reset f0h 1111 0000 up to 70 mhz 0 0 1(d0h) read manufacturer and device id 9fh 1001 1111 up to 70 mhz 0 0 1 to 4 read id (legacy command) 15h 0001 0101 up to 70 mhz 0 0 2 deep power-down b9h 1011 1001 up to 70 mhz 0 0 0 resume from deep power-down abh 1010 1011 up to 70 mhz 0 0 0 ultra deep power-down 79h 0111 1001 up to 70 mhz 0 0 0 t a ble 6-1. co mman d listing command opcode clock frequency address bytes dummy bytes data bytes
8 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 7-1. read array - 03h opcode figure 7-2. read array - 0bh opcode 7.2 dual-output read array the dual-output read array command is simila r to th e standard read array command and can be used to sequentially read a continuous stream of data from the device by simply p r oviding the clock s i gna l once the initial starting addre s s has been specified. unlike the standard read array command, however, the dual-outp u t read array command allows two bits of data to be clocked out of the device on every clock cycle, rather than just one. the dual-output read array command can be used at any clock frequency, up to the maximum specified by f rddo . to perform the dual-output read array operation, the cs pin must first be asserted and then the opcode 3bh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. following the three address bytes, a single dummy byte must also be clocked into the device. after the three address bytes and the dummy byte have been cl ocked in, additional clock cycles will result in data being output on both the so and sio pins. the data is always output with the msb of a byte first and the msb is always output on the so pin. during the first clock cycle, bit seven of the first data byte is output on the so pin, while bit six of the sam e data byte is output on the sio pin. during the next clock cycle, bits five and four of the first data byte are output on the so and sio pins, respectively. the sequence continues with each byte of data being output after every four clock cycles. when the last byte (fffffh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array.deasserting the cs pin will te rminate t he read operation and put the so and sio pins into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. sck cs si so msb msb 23 1 0 00000011 67 5 41 0 1 1 9 81 2 3 7 3 8 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte 1 high-impedance k s i o msb msb 23 1 0 00001011 67 5 41 0 1 1 9 81 2 3 9 4 2 4 3 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care data byte 1 high-impedance
9 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 7-3. dual-output read array 8. program and erase commands 8.1 byte/page program the byte/page program command allows anywhere from a singl e byte of data to 256 bytes of data to be programmed into previously erased memory locations. an erased memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 12 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to p e rform a byte/page program command, an opcode of 02h mu st be cloc ked into the devic e followed by the th ree addres s bytes denoting the firs t byte location o f the memory a rray to begin programmin g at. after the add ress bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. if the startin g memory add ress denoted by a23-a0 does not fall on an even 256-byte pag e boundary (a7-a0 are not a l l 0), then special circumstances regarding which memory locations to be programmed will apply. in this situation, any dat a that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the s a me page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, t hen the first two bytes of data w ill be prog rammed a t addresses 0000feh and 0000ffh while the last byte of data will be prog rammed a t address 000000h. the remaining bytes in the pag e (addresses 000001h through 0000fdh ) will not b e prog rammed and will remain in the e r ased s t at e (ffh). in addition, if more th an 256 bytes of data are sent to t he device, then only the last 256 bytes sent will be latched into the internal bu ffer. when the cs pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting addr ess specified by a23-a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. in addition, if the memory is in the protected state (see ?block protection? on page 13 ), then the byte/page program command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin not being deasserted on byte boundaries, or because the memory location to be programmed is protected. 6&. &6 6,6,2 62 06% 06% 23&2'( $$$$ $$$ $$ 06% ;;;;;;;; 06% 06% 06% ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' $''5(66%,76$$ '21
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10 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point befo r e the prog ram cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorp orates an intelligent programming algorit hm that can detect when a byte location fails to program properly. if a programming error arises, it will be i ndicated by the epe bit in the status register. figure 8-1. byte program figure 8-2. page program 8.2 page erase the page erase comman d c a n be used to individually erase any page in the main memory array. the main memory byte/page program command can be utilized at a later time. to p e rform a page erase with the standard page siz e (256 bytes), an opcode of 81h must be clocked into the device followed by t h ree address bytes comprised of eight dummy bits, 8 page address bits (pa7 - pa0) that specify the page in the main memory to be erased, and eight dummy bits. when a low-to-high transition occurs on the cs pin, the device will erase the selected page (the erased state is a logic 1). the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the rdy /busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly . if an erase error arises, it will be indicated by the epe bit in the status register. 8.3 block erase a block of 4 or 32 kbytes can be erased (all bits set to the logical ?1? state) in a single operation by using one of three different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, and an opcode of 52h or sck cs si so msb msb 23 1 0 00000010 67 5 41 0 1 1 9 81 2 3 9 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aaaa aaa a a msb ddddddd d address bits a23-a0 data in sck cs si so msb msb 23 1 0 00000010 67 5 49 83 9 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n
11 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 d8h is used for a 32-kbyte erase. before a block erase command c a n be started, the write enable command must have been previously issued to the device to set the wel bi t of the status register to a logical ?1? state. to perform a block erase, the cs pin must first be asserted and the appropriate opcode (20h, 52h, or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4- or 32-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deasserted, th e device will erase the appropriate block. the erasing of the block is internally self-timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. therefore, for a 4-kbyte erase, address bits a11-a0 will be ignored by the device and their values can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14-a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operat ion and no erase operation will be performed. if the memory is in the protected state, then the block erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent, the cs pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t blke ti me to determine if the device has finis h ed erasing. at s o me point before the erase cycle c o mpletes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly . if an erase error occurs, it will be indicated by the epe bit in the status register. figure 8-3. block erase 8.4 chip erase the entire memory array can be erased in a single operation by using the chip erase comma nd. before a ch ip erase comma nd c a n be s t a r ted, the write enab le command must have been prev iously issued to the device to set the wel bit of the status register to a logical ?1? state. three opcodes (60h, 62h, and c7h) can be used for the chip erase command. there is no difference in device functionality when utilizing the three opcodes, so they can be used interchangeably. to perform a chip erase, one of the three opcodes must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of t he device is internally self-timed and should take place in a time of t chpe . sck cs si so msb msb 23 1 0 cccccccc 67 5 41 0 1 1 9 81 2 3 1 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
12 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. in addition, if the memory array is in the protected state, then the chip erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status re gister will be reset back to the logical ?0? state if the cs pin is deasserted on uneven byte boundaries or if the memory is in the protected state. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t chpe time to determine if the device has finis h ed erasing. at s o me point before the erase cycle c o mpletes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly . if an erase error occurs, it will be indicated by the epe bit in the status register. fig u re 8 - 4. ch ip er ase 9. protection commands and features 9.1 write enable the write enable comma nd is u s ed to set the write enable latch (wel) bit in the status register to a logical ?1? s t ate. the wel bit must be set before a byte/page program, erase, program otp security regis t e r , or write status regis t e r comma nd can be executed. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or errone ously executed. if the wel bit in the status register is not set prior to the issuance of one of these commands, then the command will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. sck cs si so msb 23 1 0 cccccccc 67 5 4 opcode high-impedance
13 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 9-1. write enable 9.2 write disable the write disable command is used to reset the write enable lat ch (wel) bit in the status register to the logical ?0? state. with the wel bit reset, all byte/page program, erase, program otp security register, and write status register commands will not be executed. other conditions can also caus e the wel bit to be reset; for more details, refer to the wel bit section of the status register description. to issue the write disable command, the cs pin must first be asserted and the opcode of 04h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-2. write disable 9.3 block protection the device can be s o f tware protected against erroneous or ma licious program o r erase operations by utilizing the block protection feature of the device. block protection can be enabled or disabled by using the write status register comma nd to change the value of the block protection (bp0) bit in the status reg i ster. the following table outlines the two states of the bp0 bit and the a s sociated protection area. sck cs si so msb 23 1 0 00000110 67 5 4 opcode high-impedance sck cs si so msb 23 1 0 00000100 67 5 4 opcode high-impedance t a ble 9- 1. me mory arra y prote c t i o n protection level bp0 protected memory address n one 0 none full memory 1 00000h - 00ffffh
14 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 when the bp0 bit of the status register is in the logical ?1? state, the entire memory array will be protected against program or erase operations. any attempts to send a byte /page program command, a block erase command, or a chip erase command will be ignored by the device. as a safeguard against accidental or erroneous protecting or u nprotecting of the memory array, the bp0 bit itself can be locked from updates by using the wp pin and the bpl (block protection locked) bit of the status register (see ?protected states and the write protect pin? on page 14 for more details). the bp0 bit of the status register is a nonvolatile bit; ther efore, the bp0 bit will retain its state even after the device has been power cycled. care should be taken to ensure that bp0 is in the logical ?1? state before powering down for those applications that wish to have the memory array fully protected upon power up. the default state for bp0 when shipped from adesto is ?0?. 9.4 protected states and the write protect pin the wp pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. instead, the wp pin, in conjunction with the bpl (block protection locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met-the wp pin must be asserted and the bpl bit must be in the logical ?1? state. when hardware locking is active, the block protection (bp0) bit is locked and the bpl bit itself is also locked. therefore, if the memory array is protected, it will be locked in the protected state, and if the memory array is unprotected, it will be locked in the unprotected state. these states cannot be changed as long as hardware locking is active, so the write status register command will be ignored. in order to modify the protection status of the memory array, the wp pin must first be deasserted, and the bpl bit in the status register must be reset back to the logical ?0? state using the write status register command. if the wp pin is permanently connected to gnd, then once the bpl b i t is set to a logical ?1?, the on ly way to reset the bit back to the logical ?0? state is to power-cycle the device. this allows a sys te m to power-up w i th all sectors software prot ec te d but not hardware lo c k ed. therefore, sector s can be unprotected and protected as nee ded and then hardware locked at a later time by simply setting the bpl bit in the status register. when the wp pin is deasserted, or if the wp pin is permanently connected to v cc , the bpl bit in the status register can be set to a logical ?1?, but doing so will not lock the bp0 bit. table 9-2 details the various protection and locking states of the device. table 9-2. hardware and software locking wp bpl locking bpl change allowed bp0 and protection status 0 0 can be modified from 0 to 1 bp0 bit unlocked and modifiable using the write status register command. memory array can be protected and unprotected freely. 0 1 hardwa re locked locked bp0 bit locked in current state. the write status register command will have no affect. memory array is locked in current protected or unprotected state. 1 0 can be modified from 0 to 1 bp0 bit unlocked and modifiable using the write status register command. memory array can be protected and unprotected freely. 1 1 can be modified from 1 to 0 bp0 bit unlocked and modifiable using the write status register command. memory array can be protected and unprotected freely.
15 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 10. security commands 10.1 program otp security register the device contains a specialized otp (one-time programmabl e) security register that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. the otp security register is independent of the main flash memory array and is comprised of a total of 128 bytes of memory divided into two portions. the first 64 bytes (byte locations 0 th rough 63) of the otp security register are allocated as a one-time user-programmable space. once these 64 bytes have been programmed, they cannot be erased or reprogrammed. the remaining 64 bytes of the otp security register (byte locations 64 through 127) are factory programmed by adesto and will contain a unique value fo r each device. the factory programmed data is fixed and cannot be changed. the us e r-programma ble portion of the otp se c u rity regist er does not need to be erased before it is prog rammed. i n addition, the program otp se c u rity register command operates on the entire 64-byte user-programmable portion of the otp security register at one time. once the user-pr ogrammable space has been programmed with any number of bytes, the user-programmable space cannot be programmed again; therefore, it is not possible to only program the first two bytes of the register and then program the remaining 62 bytes at a later time. before the program otp security register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to program the otp security register, the cs pin must first be asserted and an opcode of 9bh must be clocked into the device followed by the three address bytes denoting the first byte location of the otp security register to begin programming at. since the size of the user- programmable portion of the otp security register is 64 bytes, the upper order address bits do not need to be decoded by the device. therefore, address bits a23-a6 will be ignored by the device and thei r values can be either a logical ?1? or ?0?. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in the internal buffer. if the s ta r ting memory address de noted by a23-a0 does not start at the beginning of the otp security register memory space (a5-a0 are not all 0), then special c i rcumstances regarding which otp sec u rity re gister locations to be prog rammed will apply. in this situation, any d a ta that is sent to the device tha t goes beyond the end of the 64-byte user- prog rammable space will wrap arou nd back to the beginning of t he otp security register. for example, if the starting addres s de noted by a23-a0 is 00003eh, and three b y te s of data are sent to the de v i ce, then t he first two bytes of data will be programmed at otp security r egister addresses 00003eh and 00003fh w h ile the last byte of dat a w i ll be prog rammed a t address 000000h. the remaining bytes in the otp security regis te r (addresses 000001h through 00003dh) will not be programmed and wi ll remain in the erased state (ffh). in addition, if more than 64 bytes of data are sent to the device, then only the last 64 by tes sent will be latched into the internal buffer. when the cs pin is deasserte d , the device w ill take the data stored in the internal buffer and program it into the appropriate otp security register locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 64 bytes of data were sent to the device, then the remaining bytes with in t he otp security register will not be programmed and will remain in t he erased state (ffh). the programming of the data bytes is internally self-time d and should take place in a time of t otpp . the three addres s bytes and at le as t one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and the user-programmable portion of t he otp security register will not be programmed. the wel bit in the status register will be reset back to the logica l ?0? state if the otp security register program cycle aborts table 10-1. otp security register security register byte number 0 1 . . . 62 63 64 65 . . . 126 127 one-time user programmable factory programmed by adesto
16 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the user-progr ammable portion of the otp security register was previously programmed. while the device is programming the otp security register, th e status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t otpp time to dete rmine if the data bytes have finished programming . at some point be fore the otp security register programming completes, the wel bit in the status register will be reset back to the logical ?0? state. if the device is powered-down during the otp security register program cyc le, the n the contents of the 64-b y te us e r programmable portion of the otp security regist er cannot be guaranteed and cannot be programmed again. the program otp security register c o mmand utilizes the inte rnal 256-buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. figure 10-1. program otp security register 10.2 read otp security register the otp security register can be sequentially read in a similar fashion to the read array operation up to the maximum clock frequency specified by f clk . to read the otp security register, the cs pin must first be asserted and the opcode of 77h must be c l ocked into the device. after the opcode has bee n clock e d in, the three addres s bytes must be c l ocked in to specify the starting add ress locatio n of the first byte to re ad within the otp security register. following the three address bytes, two dummy bytes must be clocked into the device before data can be output. after the three address bytes and the dummy bytes have been cl ocked in, additional cl o c k cycles wil l result i n o t p security register data being output on the so pin. when th e last byte (00007fh) of the otp security register has been read , the device w i ll continue rea d i n g back a t the beginni ng of the register (000000h). no delays will be incurred w h e n wrapping around from the end of the regist er to the beginning of the regis t er. deasserting the cs pin will terminate the read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. sck cs si so msb msb 23 1 0 10011011 67 5 49 83 9 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n
17 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 fig u re 1 0 -2. rea d ot p se cu rity re gister 1 1 . s t a tus register commands 11.1 read status register the status register can be read to determin e the device?s r eady/busy status, as we ll as the status of many other functions such as hardware locking and software protection. th e status register can be read at any time, including during a n in ternally self-timed program or erase oper a t ion . the st atus register consists of two bytes. to read the status register, the cs pin must first be asserted and the opcode of 05h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of status register byte 1 has been clocked out, the first bit (bit 7) of status register byte 2 will be clocked out. after the last bit (bit 0) of status register byte 2 has been clocked out, the sequence will repeat itself, starting again with bit 7 of status register byte 1, as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence will output new data. deasserting the cs pin will terminate the read status register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. sck cs si so msb msb 23 1 0 01110111 67 5 41 0 1 1 9 81 2 3 3 3 6 35 34 31 32 29 30 opcode aaaa aaa a axx x msb msb ddddddd d d d address bits a23-a0 msb xxxxx x don't care data byte 1 high-impedance t a ble 1 1 -1. s tatus r e gister f o r m at bit (1 ) name ty p e (2) des c ription 7 bpl bl ock protection locked r/w 0 bp 0 bi t u n l o cke d (d ef au l t ). 1 bp0 bit locked in current state when wp asserted. 6 res reserved for future us e r 0 reserved for future use. 5 epe eras e/program error r 0 era s e or p r ogram ope ra ti on was successful. 1 era se or program error detected. 4 wp p w r ite protect (wp ) pin status r 0 wp is asserted. 1 wp is deasserted. 3 res reserved for future us e r 0 reserved for future use. 2 bp0 bl ock protection r/w 0 entire m e m o ry array is unprotected. 1 enti re memory array is protected.
18 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 11.1.1 bpl bit the bpl bit is used to control whether the block protection (bp0) bit can be modified or not. when the bpl bit is in the logical ?1? state a nd the wp pin is asserte d , th e bp0 bit will be locked and cannot be modified. the memory array will be locked in the current protected or unprotected state. when the bpl bit is in the logical ?0? state, the bp0 bit wi ll be unlocked and can be modified. the bpl bit defaults to the logical ?0? state after device power-up. the bpl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is assert ed, then the bpl bit may only be changed from a logical ?0? (bp0 bit unlocked) to a logical ?1? (bp0 bit locked). in order to re s e t the bpl b i t back to a logical ?0? using the write status register command, the wp pin will have to first be deasserted. the bpl and bp0 bits are the only bits of the status register that can be user modified via the write status register command. 11.1.2 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logical ?1? state. the epe bit will not be set if an erase or program operat ion aborts for any reason such as an attempt to erase or program the memory when it is protected or if the wel bit is not set prior to an erase or program operation. the epe bit will be updated after every erase and program operation. 11.1.3 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 11.1.4 bp0 bit the bp0 bits provides feedback on the software protection status for the device. i n addition, the bp0 bit can also be modified to change the state of the software protection to allow the entire memory array to b e protected or unprotected. when the bp0 bit is in the logical ?0? state, then the entire memory array is unprotected. when the bp0 bit is in the log i cal ?1? state, then the entire memory array is protected against program and erase operations. 11.1.5 wel bit the wel bit indicates the current status of the internal writ e enable latch. when the wel bit is in the logical ?0? state, the device will not accept any byte/page program, erase, program otp security register, or write status register commands. the wel bit defaults to the logical ?0? state afte r a device power-up or reset oper ation. in addition, the wel bit will be reset to the logical ?0? state automatically under the following conditions: ? w r ite dis ab le o peration completes successfully ? write status register operation completes successfully or aborts 1 wel write enable latch status r 0 device is not write enabled (default). 1 device is write enabled. 0 rdy /bsy ready/busy status r 0 device is ready. 1 device is busy with an internal operation. 1. only bit s 7 and 2 of the s t atus register can be modified when using the w r ite s t a tus register command. 2. r/w = readable and writ able ? r = reada ble only t a ble 1 1 -1. s tatus r e gister f o r m at bit (1) name type (2) description
19 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 ? program otp security register operation completes succes s fully or abort s ? by te /page program operation completes successfully or abort s ? block erase operation completes success fu lly or abort s ? chip erase operation completes successfully or aborts ? hold condition aborts if the wel bit is in the logical ?1? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete o r unrecognized opcode being clocked into the device before the cs pin is de as serted. in order for the wel bit to be reset when an operation aborts pre m aturely, the entire opcode fo r a byte/page program, erase, program otp security register, or write status register co mmand must have been clocked into the device. 11.1.6 rdy /bsy bit the rdy/bsy bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. to poll the rdy /bsy bit to detect the completion of a program or erase cycle, new status register data must be continually clocked out of the device until the state of the rdy /bsy bit changes from a logical ?1? to a logical ?0?. note that the rdy /bsy bit can be read either from status regist er byte 1 or from status register byte 2. 11.1.7 rste bit the rste bit is used to enable or disable the reset comman d . when the rste bit is in th e logical 0 s t a t e (the default state after power-up), the reset command is disabled and any attempts t o reset the device using the reset command will be ignored. when the rste bit is in the logical 1 state, the reset command is enabled. the rste bit will reta in its state as long as power is a pplied t o the device. onc e s e t to the logical 1 state, the rste bit will remain in that state until it is modified using the write status regis te r byte 2 command or unt i l the de v i ce has been power cycled. the r e set command itself wi ll not change t he state of the rste bit. table 11-2. status register format ? byte 2 bit (1) 1. only bits 4 and 3 of status register byte 2 will be modified when using the write status register byte 2 command na me ty p e (2) 2. r/w = readable and w r iteable ? r = readab le o n ly. desc ription 7 res reserved for future use r 0 reserved for future use 6 res reserved for future use r 0 reserved for future use 5 res reserved for future use r 0 reserved for future use 4 rste reset enabled r/ w 0 reset command is disabled (default) 1 reset command is enabled 3 res reserved for future use r 0 reserved for future use 2 res reserved for future use r 0 reserved for future use 1 res reserved for future use r 0 reserved for future use 0 rdy /bsy ready/busy status r 0 device is ready 1 device is busy with an internal operation
20 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 fi g u re 1 1 -1. r ea d status re gi ster ? 11.2 write status register the write status register command is us e d to modify the bpl bit and the bp0 bit of the status register. before the write status register command can be is sued , the write enable command must have been previously iss u ed to set the wel bit in the status register to a logical ?1?. to issue the write status register command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. the one byte of data consists of the bpl bit value, four don?t care bits, the bp0 bit value, and two additional don?t care bits (see table 11-3 ). any additional data bytes that are sent to the device will be ignored. when the cs pin is deasserted, the bpl bit and the bp0 bit in the status register will be modified, and the wel bit in the status register will be reset back to a l ogical ?0?. the value of bp0 and the state of the bpl bit and the wp pin before the write status register command was executed (the prior state of the bpl bit and the state of the wp pin when the cs pin is deasserted) will determine whether or not software protection will be changed. please refer to section 9.4, ?protected st ates and the write protect pin? on page 14 for more details. the complete o ne byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the bpl and bp0 bits will not change, memory protection status will not change, and the wel bit in the status register will be reset back to the logical ?0? state. if the wp pin is asserted, then the bpl bit can only be set to a logical ?1?. if an attempt is made to reset the bpl bit to a logical ?0? while the wp pin is asserted, then the write status register byte command will be ignored, and the wel bit in the status register will be reset back to the logical ?0? state. in order to reset the bpl bit to a logical ?0?, the wp pin must be deasserted. sck cs si so msb 23 1 0 00000101 67 5 41 0 1 1 9 81 2 21 22 17 20 19 18 15 16 13 14 23 24 opcode msb msb dddddd dd d d msb dddddd d d status register byte1 status register byte2 high-impedance ta ble 1 1 - 3 . write status re giste r fo rma t bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bpl x x x x bp0 x x
21 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 11-2. write status register 11.3 write status register byte 2 the write status register byte 2 command is used to mo di fy the rste. using the write status register byte 2 comma nd is th e only way to modify the rste in the statu s register during normal device ope ration. bef ore the write status register byte 2 command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical 1. to issue the write status register byte 2 command, the cs pin must first be asserted and then the opcode 31h must be clocked into the device followed by one byte of data. the one byte of data consists of three don?t-care bits, the rste bit value, and four additional don?t-care bits (see table 11-4 ). any additional data bytes sent to the device will be ignored. when the cs pin is deasserted, the rste bit in the status regist er will be modified, and the wel bit in the status register will be reset back to a logical 0. the complete one byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the rste bit will not change, and the wel bit in the status register will be reset back to the logical 0 state. figure 11-3. write stat us register byte 2 sck cs si so msb 23 1 0 0000000 67 5 4 opc o d e 10 11 9 81415 13 12 1 msb dx x x x dx x status register in high-imped ance t a ble 1 1 -4. w r i te statu s r e giste r b y te 2 fo rmat bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x rste x x x x sck cs si so msb 23 1 0 0011000 67 5 4 opcode 10 11 9 81 4 1 5 13 12 1 msb xxx d xxx x status register in byte 2 high-impedance
22 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 12. other commands and functions 12.1 read manufacturer and device id identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jede c defined manufacturer id, the vendor specific device id, and the vendor specific extended device information. since not all flash devices are capable of operating at ve ry high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure all devices used in the application can be identified properly. once the identification process is complete, the application can increase the clock frequency to accommodate specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte output will be the extended device information string length, which will be 00h indicating that no extended device information follows. after the extended device information string length byte is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional.deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 12-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 65h 3 device id (part 2) 01h 4 extended device information string length 00h table 12-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex va l u e details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for adesto) 0 0 0 1 1 1 1 1 device id (part 1) family code density code 65h family code : 0 1 1 ( a t25dn x xx ser i es) ? density code: 00101 ( 512-kbit) 0 1 1 0 0 1 0 1 device id (part 2) sub code product version code 01h sub code: 000 (s t andar d series) ? product v e rsion:0 0001 0 0 0 0 0 0 0 1
23 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 12-1. read manufacturer and device id 12.2 read id (legacy command) identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the preferred method for doing so is the jedec standard ?read manufacturer and device id? method described in section 12.1 on page 22 ; however, the legacy read id command is supported on the AT25DN512C to enable backwards compatibility to previous generation devices. to read the identification information, the cs pin must first be as serted and the opcode of 1 5h must be clocked into the device. after the opcode has been clo c ked in, the device will begin output ting the identification data on the so pin during the subsequ ent clock cycles . the fi rst byte that wi ll b e output will be the manufacturer id of 1fh foll o w ed by a single byte of data representing a device code of 65h. after the device code is output, the so pin will go into a high-impendan c e state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. deasserting the cs pin will terminate the read id operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data read. figure 12-2. read id (legacy command) 12.3 deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted a nd no internal operation is in progress . the deep power-down c o mmand offers the ability to place the device into an even lower power consumption state called the deep power-down mode. sck cs si so 6 0 9fh 8 7 38 op c od e 1fh 65h 01h 00h manufacturer id device id byte 1 device i d byte 2 extended device information string length high-imped ance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits) sck cs si so msb 23 1 0 00010101 67 5 41 0 1 1 9 81 2 2 1 2 2 17 20 19 18 15 16 13 14 opcode msb 01111 1 0 0 msb 10010 1 1 0 manufacturer id device code high-impedance
24 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 when the device is in the deep power-down mode, all co mmands including the read status register command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection me chanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte bound ary (multiples of eight bits); otherw i se, the devi c e will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power-cycle. the deep power-down command w ill be ignored if an internally self-timed ope ration suc h as a program or erase cycl e is in progress. the deep power-down command must be reissued after th e in ternally self-timed operation has been completed in order for the device to enter the deep power-down mode. figure 12-3. deep power-down 12.4 resume from deep power-down in order to exit the deep power-down mode and resume nor mal device operation, the resume from deep power-down command must be issued. the resume from deep power-down command is the only command that the device will recognized while in the deep power-down mode. to resume from the deep power-down mode, the cs pin must first be asserted and opcode of abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power-down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, or if the cs pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd
25 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 12-4. resume from deep power-down 12.5 ultra-deep power-down the ultra-deep power-down mode allows the device to further reduce its energy consumption compared to the existing standby and deep power-down modes by shutting down additional internal circuitry. when the device is in the ultra- deep power-down mode, all commands including the status register read and resume from deep power-down commands will be ignored. since all commands will be ignored, the mode can be used as an extra protection mechanism against inadvertent or unintentional program and erase oper ations. entering the ultra-deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode 79h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the ultra-deep power-down m ode within the maximum time of t eudpd the complete opcode must be clocked in before the cs pin is deasserted; otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power cycle. the ultra-deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
26 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 12-5. ultra -deep power-down 12.6 exit ultra-deep power-down to exit from the ultra-deep power-down mode, any one of three operations can be performed: chip select toggle the cs pin must simply be pulsed by asserting the cs pin, waiting the minimum necessary t cslu time, and then deasserting the cs pin again. to facilitate simple software development, a dummy byte opcode can also be entered while the cs pin is being pulsed; the dummy byte opcode is simply ignored by the device in this case. after the cs pin has been deasserted, the device will exit from the ultra-deep power-down mode and return to the standby mode within a maximum time of t xudpd if the cs pin is reasserted before the t xudpd time has elapsed in an attempt to start a new operation, then that operation will be ignored and nothing will be performed. figure 12-6. exit ultra-deep power-down (chip select toggle) sck cs si so msb i cc 23 1 0 0 67 5 4 opcode high-impedance ultra-deep power-down mode current active current standby mode current t eudpd 1111001 cs so i cc high-impedance ultra-deep power-down mode current active current standby mode current t xudpd t cslu
27 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 chip select low by asserting the cs pin, waiting the minimum necessary t xudpd time, and then clocking in the first bit of the next opcode command cycle. if the first bit of the next command is clocked in before the t xudpd time has elapsed, the device will exit ultra deep power down, however the intended operation will be ignored. figure 12-7. exit ultra-deep power-down (chip select low) power cycling the device can als o exit the ultra deep power mode by power cy cling the device. the system must wait for the device to retu rn to th e standby mode before normal command operations can be resumed. upon recovery from ultra deep power down all internal registers will be at there power-on default state. 12.7 hold the hold pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. therefore, if an erase cycle is in progress, asserting the hold pin will not pause the operation, and the erase cycle will continue until it is finished. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won?t be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pin will be in a high-impe dance state. in addition , both the si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the hold pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, then the ho ld mode won?t end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still ass e rted, then any operation that may have been started will be aborted, and the device will reset the wel bit in t he status register back to the logical ?0? state. cs so i cc high-impedance ultra-deep power-down mode current active current t xudpd
28 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 12-8. hold mode 12.8 reset in some applications, it may be necessary to prematurely terminate a program or erase operation rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. the reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state. since the need to reset the device is immediate, the write enable command does not need to be issued prior to the reset command. therefore, the reset command operates i ndependently of the state of the wel bit in the status register. the reset command can be executed only if the command has been enabled by setting the reset enabled (rste) bit in the status regis te r to a logical 1 using write status register byte 2 command 31h. this command should be ente r ed before a progra m command is entered. if the reset command ha s no t been enabled (the rste bit is in the lo gical 0 state), t hen any attempts at executing the reset command w ill be ignored. to perform a reset, the cs pin must first be asserted, and then the opcode f0h must be clocked into the device. no address bytes need to be clocked in, but a confirmation byte of d0h must be clocked into the device immediately after the opcode. any additional data clocked into the device afte r the confirmation byte will be ignored. when the cs pin is deasserted, the program operation currently in progress will be terminated within a time of t swrst . since the program or erase operation may not complete before the device is reset, the contents of the page being programmed or erased cannot be guaranteed to be valid. the reset command has no effect on the states of the configuration register or rste bit in the status register. the wel however, will be reset back to its default state. the complete opcode and confirmation byte must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no reset operation will be performed. figure 12-9. reset sck cs hold hold hold hold sck cs si so msb 23 1 0 1111000 67 5 4 opcode confirmation byte in 10 11 9 81 4 1 5 13 12 0 msb 1101000 0 high-impedance
29 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 13. electrical specifications 13.3 dc characteristics 13.1 absolute maximum ratings* t e mpe r ature und er bi as. . . . . . . . - 55 ? c to + 1 25 ? c *notice: s t ress es beyond those listed under ?absolute m a ximu m r a tings ? m a y cause perm anent damage to the dev ice. this is a stress rating only and functional op eration of the device at these or any other conditions beyond those indi cated in the operational sections o f this specificat ion is not im plied. e x pos ure to abs olute maxim um rati ng conditions for extended pe riods may af fect device reliability . s t orage t e mp erature . . . . . . . . . . - 65 ? c to + 1 50 ? c all inp u t v o lt age s ? (in c ludi ng nc pins) ? wit h respect to g r ound . . . . . . . . . . - 0. 6v to + 4 . 1 v all output v o lt a ges ? wit h respect to g round . . . . . . -0.6v t o v cc + 0. 5 v 13.2 dc and operating rang e AT25DN512C op erating t e mp erature (case) ind. -40 ? c to 85 ? c v cc power supply 2.3v to 3.6v symbol parameter condition 2.3v to 3.6v unit s min typ max i udpd ultr a -deep power-down current all in put s at 0v or v cc 0.35 1 a i dp d deep pow e r-down current cs , ho l d , wp = v ih ? all in put s a t cmos le ve ls 5 12 a i sb s t and by c u rrent cs , ho l d , wp = v ih ? all in put s a t cmos le ve ls 25 40 a i cc 1 (1) active cu rre n t, lo w power r e a d (0 3h , 0b h) ope r ati o n f = 1mhz; i out = 0ma 6 9 ma f = 20mhz; i ou t = 0ma 7 10 ma i cc 2 (1) ? a c tive cur r ent , ? read operation f = 50mhz; i out = 0ma 10 12 ma f = 85mhz; i ou t = 0ma 12 15 ma i cc 3 (1) a c tive cur rent , ? p r og ra m op er at io n cs = v cc 10 12 ma i cc4 (1) a c tive cur rent , ? e r ase op er at io n cs = v cc 8 12 ma i li inp u t l oad cu rre n t all in put s a t cmos levels 1 a i lo outpu t lea kage cu rre n t all in put s a t cmos levels 1 a
30 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 notes: 1. t y pical values measured at 3.0v @ 25 c for the 2.3v to 3.6v ra nge.. 2. all inputs (sck, cs , wp and hold ) are guaranteed by design to be 5v toleran t. ? v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6ma; v cc = 2.3v 0.4 v v oh output high voltage i oh = -100a v cc - 0.2v v symbol parameter condition 2.3v to 3.6v units min typ max 13.4 ac characteristics - m aximum clock frequencies symbol parameter 2.3v to 3.6v units min typ max f clk maximum clock frequency for all operations ? (excluding 0bh opcode) 85 mhz f rdlf maximum clock frequency for 03h opcode (read array ? low frequency) 33 mhz f rddo maximum clock frequency for 3b opcode ? 70 mhz 13.5 ac characteristics ? all other parameters symbol parameter 2.3v to 3.6v units min typ max t clkh clock high time 4 ns t clkl clock low time 4 ns t clkr (1) clock rise time, peak-to-peak (slew rate) 0.1 v/ns t clkf (1) clock fall time, peak-to-peak (slew rate) 0.1 v/ns t csh chi p se lect high time 20 ns t csls chip select low setup time (relative to clock) 5 ns t cslh chip select low hold time (relative to clock) 5 ns t cshs chip select high setup time (relative to clock) 5 ns
31 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 t cshh chip select high hold time (relative to clock) 5 ns t ds data in setup time 2 ns t dh data in hold time 1 ns t dis (1) ou tp ut di sable time 6 ns t v output valid time 7 ns t oh output hold time 0 ns t hls hold low setup time (relative to clock) 5 ns t hlh hold low hold time (relative to clock) 5 ns t hhs hold high setup time (relative to clock) 5 ns t hhh hold high hold time (relative to clock) 5 ns t hlqz (1) hold low to output high-z 6 ns t hhqx (1) hold high to output low-z 6 ns t wps (1)(2) w r ite protect se tu p time 20 ns t wph (1)(2) w r ite protect hold time 100 ns t edpd (1) chi p select high to deep power-down 2 s t eudpd . chip select high to ultra deep power- down 3 s t swrst sof t wa re reset time 35 s 13.5 a c ch aracteristics ? all other parameters symbol parameter 2.3v to 3.6v units min typ max
32 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 notes: 1. not 100% tested (v a l ue guaranteed by design and characterization). 2. only applicable as a constraint for the w r ite s t atus register command when bpl = 1. ? note: 1 . m aximum values indicate worst-case performan c e af ter 100,000 erase/program cycles. 2. not 100% tested (v a l ue guaranteed by design and characterization). t cslu minimum chip select low to exit ultra deep power- down 20 ns t xudpd exit ul tra de ep power-down time 120 s t rdpd (1) chi p select high to standby mode 8 s 13.6 program and er ase characteristics symbol parameter 2.3v-3.6v min typ max units t pp (1) page program time (256 bytes) 1.5 5.0 ms t bp byte program time 8 s t pe page erase time 6 25 ms t blke (1) block erase time 4 kbytes 50 100 ms 32 kbytes 400 800 t chpe (1)(2) chip erase time 0.9 2.0 sec t otpp (1) otp security register program time 400 950 s t wrsr (2) write status register time 20 40 ms 13.7 power-up conditions symbol parameter min max units t vcsl minimum v cc to chip select low time 70 s t puw power-up device delay before program or erase allowed 5 ms v por power-on reset voltage 1.45 1.6 v 13.5 a c ch aracteristics ? all other parameters symbol parameter 2.3v to 3.6v units min typ max
33 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 13.8 input test waveforms and measurement levels 13.9 output test load 14. a c w a veforms figure 14-1. serial input timing figure 14-2. serial output timing ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2 ns (10% to 90%) device under test 30pf cs si sck so msb high-impedance msb lsb t csls t clkh t clkl t cshs t cshh t ds t dh t cslh t csh cs si sck so t v t clkh t clkl t dis t v t oh
34 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 figure 14-3. wp ti mi ng fo r wr ite statu s r e gi ste r c o mma nd w h e n bpl = 1 ? fi g u re 1 4-4. h o l d ti min g ? se ria l in put fi g u re 1 4-5. h o l d timing ? serial output ? wp si sck so 000 high-imped ance msb x t wps t wph cs lsb of write s t a tus registe r da t a b y t e msb of write s t a tus registe r op c od e msb of ne x t op c od e cs si sck so t hhh t hls t hlh t hhs hold high-impedance cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx
35 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 15. ordering information 15.1 ordering code detail note: the shipping carrier option code is not marked on the devices. ordering code package lead finish operating voltage max. freq. (mhz) operation range AT25DN512C-sshf-b AT25DN512C-sshf-t 8s1 nipdau 2.3v to 3.6v 85 industrial (-40c to +85c) AT25DN512C-mahf-y 8ma3 AT25DN512C-mahf-t AT25DN512C-xmhf-t 8x AT25DN512C-xmhf-b package type 8s1 8-lead, 0.150" wide, plastic gull wi ng small outline package (jedec soic) 8ma3 8-pad, 2 x 3 x 0.6 mm, thermally enhanced plasti c ultra thin dual flat no lead package (udfn) 8x 8-lead, thin small outline package
36 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 16. packaging information 16.1 8s1 ? jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? ? e e 1 1 n n top view t o p v i e w c c e1 e 1 end view a a b b l l a1 a 1 e e d d side view s i d e v i e w package drawing contact: contact@adestotech.com ? 8s1 f 5/19/10 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? w ide body), plastic gull wing small outline (jedec soic) swb
37 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 16.2 8ma3 ? udfn title drawing no. gpc rev. package drawing contact: contact@adestotech.com ? 8ma3 ycq a 8ma3, 8-pad, 2 x 3 x 0.6 mm body, 0.5 mm pitch, 1.6 x 0.2 mm exposed pad, saw singulated thermally enhanced plastic ultra thin dual flat no lead package (udfn/uson) common dimensions (unit of measure = mm) symbol min nom max note a 0.45 ? 0.60 a1 0.00 ? 0.05 b 0.20 ? 0.30 d 1.95 2.00 2.05 d2 1.50 1.60 1.70 e 2.95 3.00 3.05 e2 0.10 0.20 0.30 e ? 0.50 ? l 0.40 0.45 0.50 l3 0.30 ? 0.40 ccc ? ? 0.05 eee ? ? 0.05 8/8/08 notes: 1. all dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.05 mm. 3. warpage shall not exceed 0.05 mm. 4. package length/package width are considered as special characteristic. 5. refer to jede mo-236/mo-252 1 4 8 5 b e2 d2 8x c 0.10 mm b a r0.10 l3 0.10 ref. e 1.50 ref. r0.125 d 1 4 pin 1 id e 5 b a a1 a 0.127 ref. c c eee ccc 8x c 23 6 7 8 l //
38 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 16.3 8x-tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. h 8x e 12/8/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1 package drawing contact: contact@adestotech.com ?
39 at 25 dn 51 2c d s - 2 5 d n 5 12 c? 03 7a? 1 / 2 01 4 17. revision history revision level ? release date history a ? january 2014 initial release
corp orat e of fic e ca li fo rn ia | usa adest o headq uarte rs 12 50 bo rreg as ave nue sunny val e, ca 940 89 phone : (+1) 408. 40 0.0 578 emai l: co nt act @ ade sto t ec h.c om ? 2014 adest o t e ch nolog ies. all ri ght s reserved . / rev . : ds-25 d n5 12c?03 7a?1 /2 014 d i scl ai m e r : a des to t e chn o l o g i es c o rp or ati o n m a kes n o wa rr an ty f o r th e u se o f it s pr od uct s, o t he r tha n t h o se e xpr essl y co nt ai ne d i n the com p an y's st a n d a rd wa rran t y wh ich i s d e t a i l ed in a d esto' s t e rms a n d c ond i t i o n s l o cat e d on the c o m p an y's w e b si te. the c o m p any assu me s no r e sp on sib i li ty for a n y e r ro rs wh i ch m a y ap pe ar i n t h i s do cumen t, r e serves the ri g h t to chan ge de vices o r spe ci f i ca t ion s d e t a i l e d h e r e i n at a n y ti m e w i t ho ut n o ti ce , and do es no t m a ke a n y co mm i t m e n t to u p d a te the in for m a t i o n co nt ai ne d he r e i n . n o l i c en ses to p a te nt s or oth e r i n te ll e ctua l p r ope r ty of a d est o ar e g r ant ed b y the co mp a n y in c o n n e c ti on wit h t h e s a le of a d e st o pr od uc ts , e xpr es sl y o r by im pli cat io n. a d e sto ' s pr od uc ts are no t a u th o r iz e d f o r u se as critical c o mpo nen t s i n life supp ort d e vice s or syst ems. ades to ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners.

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